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Designing Embedded Processors / A Low Power Perspective, Henkel Jörg, Parameswaran Sri



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: Henkel Jörg, Parameswaran Sri
 Designing Embedded Processors / A Low Power Perspective
: Springer
:

ISBN: 1402058683
ISBN-13(EAN): 9781402058684
/: Hardback
: 568
: 1.015 .
: 01.07.2007
: English
: Illustrations
: 23.80 x 16.43 x 2.77
: Postgraduate, research & scholarly
: A low power perspective
: Link
:
:
: As we embrace the world of personal, portable, and perplexingly complex digital systems, it has befallen upon the bewildered designer to take advantage of the available transistors to produce a system which is small, fast, cheap and correct, yet possesses increased functionality.Increasingly, these systems have to consume little energy. Designers are increasingly turning towards small processors, which are low power, and customize these processors both in software and hardware to achieve their objectives of a low power system, which is verified, and has short design turnaround times.Designing Embedded Processors examines the many ways in which processor based systems are designed to allow low power devices. It looks at processor design methods, memory optimization, dynamic voltage scaling methods, compiler methods, and multi processor methods. Each section has an introductory chapter to give a breadth view, and have a few specialist chapters in the area to give a deeper perspective. The book provides a good starting point to engineers in the area, and to research students embarking upon the exciting area of embedded systems and architectures.
: : 235x155
: Researchers in the area of design automation of systems, engineers, design automation specialists, designers of digital embedded SW/HW specialists
: Low Power systems
HW/SW codesign
Embedded Processors
: eng





Advanced Memory Optimization Techniques for Low-Power Embedded Processors

: Verma Manish, Marwedel Peter
: Advanced Memory Optimization Techniques for Low-Power Embedded Processors
ISBN: 1402058969 ISBN-13(EAN): 9781402058967
: Springer
:
: 15625 .
  : .

: The design of embedded systems warrants a new perspective because of the following two reasons: Firstly, slow and energy inefficient memory hierarchies have already become the bottleneck of the embedded systems. It is documented in the literature as the memory wall problem. Secondly, the software running on the contemporary embedded devices is becoming increasingly complex. It is also well understood that no silver bullet exists to solve the memory wall problem. Therefore, this book explores a collaborative approach by proposing novel memory hierarchies and software optimization techniques for the optimal utilization of these memory hierarchies. Linking memory architecture design with memory-architecture aware compilation results in fast, energy-efficient and timing predictable memory accesses.The evaluation of the optimization techniques using real-life benchmarks for a single processor system, a multiprocessor system-on-chip (SoC) and for a digital signal processor system, reports significant reductions in the energy consumption and performance improvement of these systems. The book presents a wide range of optimizations, progressively increasing in the complexity of analysis and of memory hierarchies. The final chapter covers optimization techniques for applications consisting of multiple processes found in most modern embedded devices.Advanced Memory Optimization Techniques for Low Power Embedded Processors is designed for researchers, complier writers and embedded system designers / architects who wish to optimize the energy and performance characteristics of the memory subsystem.

On-line Error Detection and Fast Recover Techniques for Dependable Embedded Processors

: Pflanz Matthias
: On-line Error Detection and Fast Recover Techniques for Dependable Embedded Processors
ISBN: 354043318X ISBN-13(EAN): 9783540433187
: Springer
:
: 7314 .
  : .

: This book presents a new approach to on-line observation and concurrent checking of processors by refining and improving known techniques and introducing new ideas.The proposed on-line error detection and fast recover techniques support and complement other established methods. In combination with other on-line observation priniciples and with a combined hardware-software test, these techniques are used to fulfill a complete self-check scheme for an embedded processor.

Multiscalar Processors

: Franklin Manoj
: Multiscalar Processors
ISBN: 1402072864 ISBN-13(EAN): 9781402072864
: Springer
:
: 14629 .
  : .

: Research on the Multiscalar execution model was introduced in the early 1990's, recognizing the inadequacies of relying entirely on Instruction Level Parallelism (ILP). The goal was to augment the parallelism bridgehead established by ILP with the ground forces of Thread-Level Parallelism (TLP), a coarser form of parallelism. Many studies on parallelism indeed confirm the significant performance potential of executing multiple threads of a program in parallel. The difficulties that have been plaguing the parallelization of ordinary, non-numeric programs for decades have been complex flows of control and ambiguous data dependences through memory. The breakthrough provided by the Multiscalar execution model was the use of speculative threads along with data speculation. Speculative threads allow sequential programs to be parallelized, and data speculation allow threads to be executed in parallel even if they are likely to have data dependences. Multiscalar Processors presents a comprehensive treatment of the basic principles of Multiscalar execution, and advanced techniques for implementing the Multiscalar concepts. Special emphasis is placed on highlighting the major challenges involved in Multiscalar processing. This book is organized into nine chapters, and provides an excellent synopsis of a large body of research carried out on multiscalar processors in the last decade. It starts with technology trends that provide an impetus to the development of multiscalar processors and shape the development of future processors. The work ends with a review of the recent developments related to multiscalar processors. Multiscalar Processors is designed to meet the needs of a professional audience composed of designers and programmers of next-generation processors and researchers in computer architecture and engineering. This book is also suitable as a secondary text for graduate level students in computer science and engineering.

Guide to RISC Processors / for Programmers and Engineers

: Dandamudi Sivarama P.
: Guide to RISC Processors / for Programmers and Engineers
ISBN: 0387210172 ISBN-13(EAN): 9780387210179
: Springer
:
: 9404 .
  : .

: Recently, there's been a trend toward processors based on the RISC (Reduced Instruction Set Computer) design: Some example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel’s 64-bit processor Itanium.This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM and Itanium.  Initial chapters explain the differences between the CISC and RISC designs, and one clearly discusses the RISC design principles.  Roughly the second half of the book is dedicated to MIPS assembly language programming, thereby enabling readers to grasp the concepts discussed in the first half.Topics and features:*Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience*Presents material in a manner suitable for self-study, using several examples in each chapter• Assembly language programs permit reader executables using the SPIM simulator• Integrates core concepts to processor designs and their implementations• Supplies extensive programming examples and figures• Each chapter begins with an overview and ends with a summary Guide to RISC Processors provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language.  Professionals and programmers seeking an authoritative and practical overview of RISC processors will find the guide an essential resource, and students in computer architecture and other courses will regard it as an important reference tool.

Dedicated Digital Processors: Methods in Hardware/Software Co-Design

: F. Mayer-Lindenberg
: Dedicated Digital Processors: Methods in Hardware/Software Co-Design
ISBN: 0470844442 ISBN-13(EAN): 9780470844441
: Wiley
:
: 12359 .
  : .

: The evolution of digital technology has resulted in the design of digital processors with increasingly complex capabilities. Intended as an introduction to the subject, this book presents an integrated and accessible approach to the design and implemention of digital processors. Dedicated Digital Processors emphasizes the common aspects of hardware and software structures, explaining the opportunities provided for developing low-power, high-speed processors and processor networks. Features include: An introduction to the technological basics of digital computers, including transistor circuits and the properties of current integrated chips. Discussions on complexity issues such as minimization, the timing and synchronization of computations and techniques used to boost performance in modern high-speed processors. The presentation of a programmable processor design, including the handling of input and output, interrupt processing and DMA. A detailed evaluation of standard DSP architectures including up-to-date information on TI 67xx, Analog Devices, Sharc processors and Virtex FPGA (field programmable gate arrays). VHDL examples and exercises that can be simulated and synthesized with free design tools provided by FPGA companies. Based on the author's considerable experience in teaching digital systems design and digital signal processing, this book is an excellent reference for graduate and senior undergraduate students in electronic and computer engineering. Practising engineers and professionals developing DSP applications will appreciate the guidance to designing digital systems.

Embedded DSP Processor Design,2

: Dake Liu
: Embedded DSP Processor Design,2
ISBN: 0123741238 ISBN-13(EAN): 9780123741233
: Elsevier Science
:
: 7832 .
  : .

: This book provides design methods for Digital Signal Processors and Application Specific Instruction set Processors, based on the author's extensive, industrial design experience. Top-down and bottom-up design methodologies are presented, providing valuable guidance for both students and practicing design engineers. Coverage includes design of internal-external data types, application specific instruction sets, micro architectures, including designs for datapath and control path, as well as memory sub systems. Integration and verification of a DSP-ASIP processor are discussed and reinforced with extensive examples.

Embedded Processor-Based Self-Test

: Gizopoulos Dimitris, Paschalis A., Zorian Yervant
: Embedded Processor-Based Self-Test
ISBN: 1402027850 ISBN-13(EAN): 9781402027857
: Springer
: 17760 .
  : .

: Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design.Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment.Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.

Programming Massively Parallel Processors,

: David Kirk
: Programming Massively Parallel Processors,
ISBN: 0124159923 ISBN-13(EAN): 9780124159921
: Elsevier Science
:
: 5638 .
  : .

Customizable  Embedded Processors,V

: Paolo Ienne
: Customizable Embedded Processors,V
ISBN: 0123695260 ISBN-13(EAN): 9780123695260
: Elsevier Science
:
: 6265 .
  : .

: Customizable processors have been described as natural steps in the evolution of the microprocessor business. This book explores a trend to build methodologies to tailor-fit processors to the specific needs of different products. It addresses the goal of maintaining processors, at a cost comparable to that of maintaining a single processor.

Low-Power Processors and Systems on Chips

: Christian Piguet
: Low-Power Processors and Systems on Chips
ISBN: 084936700X ISBN-13(EAN): 9780849367007
: Taylor&Francis
:
: 11202 .
  : .

: The power consumption of microprocessors is one of the most important challenges of high-performance chips and portable devices. In chapters drawn from Piguet's recently published "Low-Power Electronics Design", this volume addresses the design of low-power microprocessors in deep submicron technologies. It provides a focused reference for specialists involved in systems-on-chips, from low-power microprocessors to DSP cores, reconfigurable processors, memories, ad-hoc networks, and embedded software.

"Low-Power Processors and Systems on Chips" is organized into three broad sections for convenient access. The first section examines the design of digital signal processors for embedded applications and techniques for reducing dynamic and static power at the electrical and system levels. The second part describes several aspects of low-power systems on chips, including hardware and embedded software aspects, efficient data storage, networks-on-chips, and applications such as routing strategies in wireless RF sensing and actuating devices.

The final section discusses embedded software issues, including details on compilers, retargetable compilers, and coverification tools. Providing detailed examinations contributed by leading experts, "Low-Power Processors and Systems on Chips" supplies authoritative information on how to maintain high performance while lowering power consumption in modern processors and SoCs. It is a must-read for anyone designing modern computers or embedded systems.

Architecture Exploration for Embedded Processors with LISA

: Hoffmann Andreas, Meyr Heinrich, Leupers Rainer
: Architecture Exploration for Embedded Processors with LISA
ISBN: 1402073380 ISBN-13(EAN): 9781402073380
: Springer
:
: 16719 .
  : .

: The LISA processor design platform (LPDP) presented in Architecture Exploration for Embedded Processors with LISA addresses various design challenges. It addresses SoC integration issues by offering APIs for external simulation environments, as well as solutions for the problem of efficient and user-friendly heterogeneous multiprocessor debugging.

Run-time Adaptation for Reconfigurable Embedded Processors

: Bauer
: Run-time Adaptation for Reconfigurable Embedded Processors
ISBN: 1441974113 ISBN-13(EAN): 9781441974112
: Springer
:
: 13672 .
  : .

: Embedded processors are the heart of embedded systems. Reconfigurable embedded processors comprise an extended instruction set that is implemented using a reconfigurable fabric (similar to a field-programmable gate array, FPGA). This book presents novel concepts, strategies, and implementations to increase the run-time adaptivity of reconfigurable embedded processors. Concepts and techniques are presented in an accessible, yet rigorous context. A complex, realistic H.264 video encoder application with a high demand for adaptivity is presented and used as an example for motivation throughout the book. A novel, run-time system is demonstrated to exploit the potential for adaptivity and particular approaches/algorithms are presented to implement it.


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