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CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications / Design Methodology, Analysis, and Implementation, Bourdi Taoufik, Kale Izzet



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Автор: Bourdi Taoufik, Kale Izzet
Название:  CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications / Design Methodology, Analysis, and Implementation
ISBN: 9781402059278
Издательство: Springer
Классификация:
ISBN-10: 1402059272
Обложка/Формат: Hardback
Страницы: 220
Вес: 0.493 кг.
Дата издания: 02.03.2007
Серия: Analog Circuits and Signal Processing
Язык: English
Иллюстрации: Illustrations
Размер: 23.39 x 15.60 x 1.42
Читательская аудитория: Tertiary education (us: college)
Подзаголовок: Design methodology, analysis, and implementation
Ссылка на Издательство: Link
Рейтинг:
Поставляется из: Германии
Дополнительное описание: Формат: 235x155
Круг читателей: RFIC, RF, wireless IC and system design engineers and academics involved in the teaching, research, design and/or implementation of high purity and fast switching speed frequency synthesizers for various wireless applications and standards such as GSM, WL
Ключевые слова: Delta-sigma
Noise-shapping
Fractional-N
Frequency
Synthesizer
Язык: eng
Оглавление: Preface. Nomenclature.1. INTRODUCTION. 1.1. Introduction. 1.2. Research contribution. 2. WIRELESS COMMUNICATIONS SYSTEMS. 2.1. introduction. 2.2. The wireless lan standards. 2.3. Wireless lan transceiver systems.3. PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS. 3.1. Introduction. 3.2. Phase-locked loop frequency synthesizer. 3.3. Phase-locked loop parameters. 3.4. Noise in phase-locked loops. 3.5. Fractional-N synthesizers. 3.6. RMS phase error and Error Vector Magnitude (EVM). 3.7. Conclusion.4. SYSTEM SIMULATION OF delta-sigma-BASED FRACTIONAL-N FREQUENCY SYNTHESIZERS. 4.1. Introduction. 4.2. Phase domain model. 4.3. Synthesizer platform evaluation. 4.4. Conclusion. 5. MULTI-MODE D-S BASED FRACTIONAL-N FREQUENCY SYNTHESIZER. 5.1. Introduction. 5.2. An overview. 5.3. A Multi-Mode Multi-Standard Delta-Sigma Based PLL Synthesizer Design. 5.4. The Delta-Sigma Frequency Synthesizer Sub-Blocks Implementation. 5.5. Measured Performance of the implemented Synthesizer. 5.6. Summary and conclusion.6. IMPROVED PERFORMANCE FRACTIONAL-N FREQUENCY SYNTHESIZER. 6.1. Introduction. 6.2. Overview. 6.3. Delta-Sigma controlled adaptive charge pump. 6.4. Synthesizer loop calibration. 6.5. Process Calibration I/C Slew rate & RC time constant. 6.6. VCO Tuning gain calibration. 6.7. Imroved vco band switching. 6.8. Experimental Results. 6.9. Comparison with published results. 6.10. Conclusion.7. CONCLUSIONS AND FURTHER WORK. 7.1. Conclusion. 7.2. Further work. APPENDIX A. PHASE FREQUENCY DETECTORS & CHARGE PUMPS. 1. Phase-frequency detectors. 2. Charge pump. 3. PFD/CP characteristics. B. CONTROLLED OSCILLATORS. 1. Reference oscillators. 2. Voltage controlled oscillators.C. PHASE NOISE. 1. Calculation of global phase error from L(f). 2. Phase noise and phase modulation. 3. RMS phase error from phase noise. 4. Residual FM. D. FREQUENCY DIVIDERS. 1. Reference divider. 2. Feedback divider. 3. High speed CMOS divider design. 4. Implemented CML gates.E. CODES & PROGRAMS. INDEX





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