Pascal Meinerzhagen; Adam Teman; Robert Giterman; Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip 9783319604015

Варианты приобретения

Цена: 15372.00р.
Кол-во:
Наличие: Поставка под заказ. Есть в наличии на складе поставщика.
Склад Америка: Есть
При оформлении заказа до: 2025-07-28
Ориентировочная дата поставки: Август-начало Сентября
При условии наличия книги у поставщика.

Добавить в корзину

в Мои желания

Автор: Pascal Meinerzhagen; Adam Teman; Robert Giterman;
Название: Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
ISBN: 9783319604015
Издательство: Springer
Классификация:

Электроника

Схемы и компоненты

Накопители и периферийные устройства

ISBN-10: 3319604015
Обложка/Формат: Hardcover
Страницы: 146
Вес: 0.40 кг.
Дата издания: 14.07.2017
Язык: English
Издание: 1st ed. 2018
Иллюстрации: 67 tables, color; 84 illustrations, color; ix, 146 p. 84 illus. in color.
Размер: 234 x 156 x 11
Читательская аудитория: Professional & vocational
Основная тема: Engineering
Ссылка на Издательство: Link
Рейтинг:
Поставляется из: Германии
Описание: This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Дополнительное описание: Motivation.- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs).- GC-eDRAMs Operated at Scaled Supply Voltages.- Near-VT GC-eDRAM Implementations with Extended Retention Times.- Aggressive Technology and Voltage Scaling (to Sub-VT Domain).- Single-Supply

Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip, Pascal Meinerzhagen; Adam Teman; Robert Giterman;