Accelerator Programming Using Directives, Sunita Chandrasekaran; Guido Juckeland

Автор: Sunita Chandrasekaran; Guido Juckeland; Sandra Wie
Название: Accelerator Programming Using Directives
ISBN: 3030122735 ISBN-13(EAN): 9783030122737
Издательство: Springer
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Цена: 6986.00 р.
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Описание: This book constitutes the refereed post-conference proceedings of the 5th International Workshop on Accelerator Programming Using Directives, WACCPD 2018, held in Dallas, TX, USA, in November 2018. The 6 full papers presented have been carefully reviewed and selected from 12 submissions.

Автор: Huang, Hantao Yu, Hao
Название: Compact and fast machine learning accelerator for iot devices
ISBN: 981133322X ISBN-13(EAN): 9789811333224
Издательство: Springer
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Цена: 18167.00 р.
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Описание: This book presents the latest techniques for machine learning based data analytics on IoT edge devices. A comprehensive literature review on neural network compression and machine learning accelerator is presented from both algorithm level optimization and hardware architecture optimization. Coverage focuses on shallow and deep neural network with real applications on smart buildings. The authors also discuss hardware architecture design with coverage focusing on both CMOS based computing systems and the new emerging Resistive Random-Access Memory (RRAM) based systems. Detailed case studies such as indoor positioning, energy management and intrusion detection are also presented for smart buildings.

Автор: Iouliia Skliarova; Valery Sklyarov
Название: FPGA-BASED Hardware Accelerators
ISBN: 303020720X ISBN-13(EAN): 9783030207205
Издательство: Springer
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Цена: 18167.00 р.
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Описание: This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.