Li Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design 9789811985508

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Автор: Li
Название: Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design
ISBN: 9789811985508
Издательство: Springer
Классификация:

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Архитектура и логическое построение вычислительных систем

ISBN-10: 9811985502
Обложка/Формат: Hardback
Страницы: 304
Вес: 0.65 кг.
Дата издания: 02.03.2023
Язык: English
Издание: 1st ed. 2023
Иллюстрации: 4 tables, color; 1 illustrations, black and white; xviii, 304 p. 1 illus.
Размер: 235 x 155
Читательская аудитория: Professional & vocational
Основная тема: Computer Science
Подзаголовок: A self-test, self-diagnosis, and self-repair-based approach
Ссылка на Издательство: Link
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Поставляется из: Германии
Описание: With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.
Дополнительное описание: Chapter 1: Introduction.- Chapter 2: Fault-tolerant general circuits with 3S.- Chapter 3: Fault-tolerant general purposed processors with 3S.- Chapter 4: Fault-tolerant network-on-chip with 3S.- Chapter 5: Fault-tolerant deep learning processors with 3S.-

Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design, Li