VLSI Physical Design: From Graph Partitioning to Timing Closure, Andrew B. Kahng; Jens Lienig; Igor L. Markov; Jin
Автор: Vikram Iyengar; Anshuman Chandra Название: Test Resource Partitioning for System-on-a-Chip ISBN: 1402071191 ISBN-13(EAN): 9781402071195 Издательство: Springer Рейтинг: Цена: 23757.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Talks about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (SOC) test automation. This book aims to position test resource partitioning in the context of SOC test automation. It presents various techniques for the partitioning and optimization of the three major SOC test resources.
Автор: Vikram Iyengar; Anshuman Chandra Название: Test Resource Partitioning for System-on-a-Chip ISBN: 1461354005 ISBN-13(EAN): 9781461354000 Издательство: Springer Рейтинг: Цена: 13974.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Автор: S. Sapatnekar; Sung-Mo (Steve) Kang Название: Design Automation for Timing-Driven Layout Synthesis ISBN: 0792392817 ISBN-13(EAN): 9780792392811 Издательство: Springer Рейтинг: Цена: 26546.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: The automation of layout synthesis design under stringent timing specifications is essential for VLSI circuits and systems design. Through a discussion of the essential design automation process steps and important models and algorithms, this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs.
Описание: Constituting the proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, 2002, the papers have been organized into topical sections including: arithmetics; low-level modelling and characterization; asynchronous and adiabatic techniques.
Описание: Constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 full papers presented were organized in topical sections on low-power processors, code optimization for low-power, high-level design, low-power circuits, and more.
Описание: Constitutes the proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007. This work contains papers organized in topical sections on high-level design, low power design techniques, low power analog circuits and low power applications.
Описание: The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Описание: The papers in this book cover topics such as RTL power modeling, power esti mation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules.
Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri Название: Switch-Level Timing Simulation of MOS VLSI Circuits ISBN: 0898383021 ISBN-13(EAN): 9780898383027 Издательство: Springer Рейтинг: Цена: 23757.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
Автор: Ashish Srivastava; Dennis Sylvester; David Blaauw Название: Statistical Analysis and Optimization for VLSI: Timing and Power ISBN: 1441938273 ISBN-13(EAN): 9781441938275 Издательство: Springer Рейтинг: Цена: 19589.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Comprises a valuable reference for statistical analysis and optimization techniques in current and future VLSI design for CAD-Tool developers and for researchers interested in starting work in this very active area of research.
Автор: Vasant B. Rao; David V. Overhauser; Timothy N. Tri Название: Switch-Level Timing Simulation of MOS VLSI Circuits ISBN: 1461289637 ISBN-13(EAN): 9781461289630 Издательство: Springer Рейтинг: Цена: 23058.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging.
Автор: Sachin Sapatnekar Название: Timing ISBN: 1441954082 ISBN-13(EAN): 9781441954084 Издательство: Springer Рейтинг: Цена: 25853.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: 7 TIMING ANALYSIS FOR SEQUENTIAL CIRCUITS 7.1 INTRODUCTION A general sequential circuit is a network of computational nodes (gates) and memory elements (registers).
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