Описание: This volume encompasses the latest, innovative methods of testing three-dimensional integrated circuits, incorporating pre-bond and post-bond tests as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
Описание: These elements allow greatly improved levels of performance in Si monolithic low-noise amplifiers, power amplifiers, up-conversion and down-conversion mixers and local oscillators. Accurate knowledge of inductance values, quality factor (Q) and the influence of ad- cent elements (on-chip proximity effects) and substrate losses is essential.
Автор: Chuan Seng Tan; Ronald J. Gutmann; L. Rafael Reif Название: Wafer Level 3-D ICs Process Technology ISBN: 1441945628 ISBN-13(EAN): 9781441945624 Издательство: Springer Рейтинг: Цена: 26120.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology.
Автор: Swaminathan Madhavan Название: Design and Modeling for 3D ICs and Interposers ISBN: 9814508594 ISBN-13(EAN): 9789814508599 Издательство: World Scientific Publishing Рейтинг: Цена: 16790.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: 3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the Silicon Via (TSV) and Glass Via (TGV) technology, the book introduces 3DICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.
Описание: Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi- vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler.
Описание: Takes a look at coupling through the common silicon substrate, and noise at the power supply lines. This book explains the elementary knowledge needed to understand these phenomena and presents a review of works and research results. It is suitable as an introductory material to noise-coupling problems in mixed-signal ICs.
Описание: These elements allow greatly improved levels of performance in Si monolithic low-noise amplifiers, power amplifiers, up-conversion and down-conversion mixers and local oscillators. Accurate knowledge of inductance values, quality factor (Q) and the influence of ad- cent elements (on-chip proximity effects) and substrate losses is essential.
Автор: Mihai A.T. Sanduleanu; Ed A.J.M. van Tuijl Название: Power Trade-offs and Low-Power in Analog CMOS ICs ISBN: 1441949437 ISBN-13(EAN): 9781441949431 Издательство: Springer Рейтинг: Цена: 23757.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This volume concerns power, noise and accuracy in CMOS Analog IC Design. The authors show that power, noise and accuracy should be treated in a unitary way, as the three are inter-related. The book discusses all possible practical power-related specs at circuit and architecture level.
Автор: Wim Claes; Willy M Sansen; Robert Puers Название: Design of Wireless Autonomous Datalogger IC`s ISBN: 1441952705 ISBN-13(EAN): 9781441952707 Издательство: Springer Рейтинг: Цена: 19589.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Design of Wireless Autonomous Dataloggers IC`s reveals the state of the art in the design of complex dataloggers, with a special focus on low power consumption.
Описание: Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi- vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler.
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