The Art of Timing Closure: Advanced ASIC Design Implementation, Golshan Khosrow
Автор: Andrew B. Kahng; Jens Lienig; Igor L. Markov; Jin Название: VLSI Physical Design: From Graph Partitioning to Timing Closure ISBN: 9400790201 ISBN-13(EAN): 9789400790209 Издательство: Springer Рейтинг: Цена: 9781.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Автор: Himanshu Bhatnagar Название: Advanced ASIC Chip Synthesis ISBN: 1461346622 ISBN-13(EAN): 9781461346623 Издательство: Springer Рейтинг: Цена: 14365.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler (R) and PrimeTime (R) describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Автор: Himanshu Bhatnagar Название: Advanced ASIC Chip Synthesis ISBN: 1475776292 ISBN-13(EAN): 9781475776294 Издательство: Springer Рейтинг: Цена: 22203.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler (R) Physical Compiler (R) and PrimeTime (R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Описание: Constitutes the proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007. This work contains papers organized in topical sections on high-level design, low power design techniques, low power analog circuits and low power applications.
Автор: Steven S. Leung; Michael A. Shanblatt Название: ASIC System Design with VHDL: A Paradigm ISBN: 1461564751 ISBN-13(EAN): 9781461564751 Издательство: Springer Рейтинг: Цена: 15672.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Unlike ULSI whose complexity can be hidden inside a memory chip or a standard component and thus can be accommodated by traditional system design methods, ASIC requires system designers to master a much larger body of knowledge spanning from processing technology and circuit techniques to architecture principles and algorithm characteristics.
Автор: Ashok B. Mehta Название: ASIC/SoC Functional Design Verification ISBN: 3319866206 ISBN-13(EAN): 9783319866208 Издательство: Springer Рейтинг: Цена: 15372.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
Описание: The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Описание: The papers in this book cover topics such as RTL power modeling, power esti mation and optimization, system-level design, transistor level design, asynchronous circuit design, power efficient technologies, design of multimedia processing applications, adiabatic design and arithmetic modules.
Описание: Constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 full papers presented were organized in topical sections on low-power processors, code optimization for low-power, high-level design, low-power circuits, and more.
Автор: S. Sapatnekar; Sung-Mo (Steve) Kang Название: Design Automation for Timing-Driven Layout Synthesis ISBN: 0792392817 ISBN-13(EAN): 9780792392811 Издательство: Springer Рейтинг: Цена: 26546.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: The automation of layout synthesis design under stringent timing specifications is essential for VLSI circuits and systems design. Through a discussion of the essential design automation process steps and important models and algorithms, this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs.
Описание: Constituting the proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, 2002, the papers have been organized into topical sections including: arithmetics; low-level modelling and characterization; asynchronous and adiabatic techniques.
Автор: N. Bouden-Romdhane; Vijay Madisetti; J.W. Hines Название: Quick-Turnaround ASIC Design in VHDL ISBN: 0792397444 ISBN-13(EAN): 9780792397441 Издательство: Springer Рейтинг: Цена: 26546.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. This book shows a way to effectively resolve this tension by retaining the high-level conciseness of VHDL.
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