Описание: At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs.
Chapter 1. Introduction.- Chapter 2. Design Implementation Data Structures and Settings.- Chapter 3. Design Constraints Development.- Chapter 4. Multiple Modes and Multiple Corners Development.- Chapter 5. Concurrent Floor Planning and Placement.- Chapter 6. Placement and Timing Analysis.- Chapter 7. Clock Tree Synthesis and Timing Analysis.- Chapter 8. Detail Route and Timing, Power Analysis.- Chapter 9. Final Route and Timing Closure in all Modes and Corners.- Chapter 10. Functional and Physical Verification.
Описание: The complexity of modern chip design requires extensive use of specialized software throughout the process. To achieve the best results, a user of this software needs a high-level understanding of the underlying mathematical models and algorithms. In addition, a developer of such software must have a keen understanding of relevant computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. This book introduces and compares the fundamental algorithms that are used during the IC physical design phase, wherein a geometric chip layout is produced starting from an abstract circuit design. This updated second edition includes recent advancements in the state-of-the-art of physical design, and builds upon foundational coverage of essential and fundamental techniques. Numerous examples and tasks with solutions increase the clarity of presentation and facilitate deeper understanding. A comprehensive set of slides is available on the Internet for each chapter, simplifying use of the book in instructional settings. “This improved, second edition of the book will continue to serve the EDA and design community well. It is a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools and design the most advanced micro-electronics.” Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Systems Group “This is the book I wish I had when I taught EDA in the past, and the one I’m using from now on.” Dr. Louis K. Scheffer, Howard Hughes Medical Institute “I would happily use this book when teaching Physical Design. I know of no other work that’s as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!” Prof. John P. Hayes, University of Michigan “The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.” Prof. Kurt Keutzer, University of California, Berkeley “An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” Prof. Sachin Sapatnekar, University of Minnesota
Автор: Andrew B. Kahng; Jens Lienig; Igor L. Markov; Jin Название: VLSI Physical Design: From Graph Partitioning to Timing Closure ISBN: 9400790201 ISBN-13(EAN): 9789400790209 Издательство: Springer Рейтинг: Цена: 9781.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: LSI Physical Design explores how algorthims can be used to create a geometric chip layout can be created from an abstract circuit design. The text emphasizes essential, fundamental techniques, ranging from hypergraph partictioning and circuit placement to timing closure.
Автор: Himanshu Bhatnagar Название: Advanced ASIC Chip Synthesis ISBN: 1461346622 ISBN-13(EAN): 9781461346623 Издательство: Springer Рейтинг: Цена: 14365.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler (R) and PrimeTime (R) describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Автор: Himanshu Bhatnagar Название: Advanced ASIC Chip Synthesis ISBN: 1475776292 ISBN-13(EAN): 9781475776294 Издательство: Springer Рейтинг: Цена: 22203.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler (R) Physical Compiler (R) and PrimeTime (R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools.
Описание: Constitutes the proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007, held in Gothenburg, Sweden, in September 2007. This work contains papers organized in topical sections on high-level design, low power design techniques, low power analog circuits and low power applications.
Автор: Taraate Vaibbhav Название: ASIC Design and Synthesis: RTL Design Using Verilog ISBN: 9813346442 ISBN-13(EAN): 9789813346444 Издательство: Springer Рейтинг: Цена: 18167.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
Автор: Taraate Vaibbhav Название: ASIC Design and Synthesis: Rtl Design Using Verilog ISBN: 9813346418 ISBN-13(EAN): 9789813346413 Издательство: Springer Цена: 18167.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This book describes simple to complex ASIC design practical scenarios using Verilog. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies.
Автор: Steven S. Leung; Michael A. Shanblatt Название: ASIC System Design with VHDL: A Paradigm ISBN: 1461564751 ISBN-13(EAN): 9781461564751 Издательство: Springer Рейтинг: Цена: 15672.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: Unlike ULSI whose complexity can be hidden inside a memory chip or a standard component and thus can be accommodated by traditional system design methods, ASIC requires system designers to master a much larger body of knowledge spanning from processing technology and circuit techniques to architecture principles and algorithm characteristics.
Описание: The papers are organized in topical sections on variability & statistical timing, circuit level techniques, power management, low power circuits & technology, system level techniques, power & timing optimization techniques, self-timed circuits, low power circuit analysis & optimization, and low power design studies.
Автор: Ashok B. Mehta Название: ASIC/SoC Functional Design Verification ISBN: 3319594176 ISBN-13(EAN): 9783319594170 Издательство: Springer Рейтинг: Цена: 18167.00 р. Наличие на складе: Есть у поставщика Поставка под заказ.
Описание: This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.
ООО "Логосфера " Тел:+7(495) 980-12-10 www.logobook.ru
